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A Scalable Halftoning Coprocessor Architecture

A. Kugler, R.D. Hersch

Proc. IEEE Intern. Conf. on Application Specific Array Processors, (Eds. Capello et. al.), 1995, pp. 76-84

Exact-angle superscreen dithering requires large dither tiles. Since storing precomputed screen elements for each intensity level would require too much memory, dithering must be executed on the fly at halftoning time. For this purpose, a dithering coprocessor is presented which generates halftoned images at high speed. The proposed hardware architecture is based on a pipelined and scalable design which speeds up halftoning by a factor of twenty compared with modern RISC software-based solutions. We describe the architecture of the coprocessor and show to what extent it can be scaled for improving performances.

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Last modified: 2009/01/27 14:15:01